This invention relates to programmable logic arrays (PLAs), and more particularly to a unique programmable logic array utilizing emitter-coupled logic to achieve unprecedented speed, while including TTL-compatible programming circuitry in order to allow the programmable logic array device constructed in accordance with the teachings of this invention to be programmed utilizing standard, inexpensive, prior art TTL programmable logic array programmers.
Programmable logic arrays are well known in the art. Programmable logic arrays typically comprise an array of cells, each cell comprising an access means and a programmable element, such as a fuse. A plurality of such cells are connected in order to provide a product term, which is the mathematical result of a boolean equation performed on a plurality of input signals. The PLA array includes a number of cells configured in order to provide a number of such product terms operating on said input signals. Such prior art PLA devices include the PAL family of devices manufactured and sold by Monolithic Memories, Inc., the assignee of this application. PAL is a registered trademark of Monolithic Memories Inc.
There are many varieties of PLAs, primarily distinguished by their size, organization, and technology (i.e. bipolar, MOS, CMOS). In addition, "An ECL Field Programmable Logic Array," Schmitz and Hingarh, ISSCC, Issue 84 Page 264, describes an emitter coupled logic (ECL) programmable logic array. However, this ECL PLA required an extremely high amount of power (typically 4.75 watts during both programming and normal operating conditions). In addition, the above-mentioned paper did not describe an ECL PLA which could be programmed using a standard TTL PLA programmer. Accordingly power dissipation was a problem, as well as requiring very specialized and expensive equipment in order to program the PLA. Furthermore, because of the problems with programming this prior art ECL PLA, the device was very expensive. With increasing complexity and sophistication in the electronics marketplace, higher-speed PLAs have become necessary. The typical access time (i.e. the time from the application of input signals to a PLA device to the provision of product terms on the output leads of the device) are approximately 15 nanoseconds for state-of-the-art TTL PLAs, 30-40 nanoseconds for CMOS PLAs, and approximately 4 nanoseconds for ECL PLAs. Accordingly, it is desirable to provide an ECL PLA for higher speeds, yet which does not require specialized and expensive equipment for programming.